The present invention relates to a semiconductor device and a semiconductor designing apparatus, and more particularly, to a semiconductor device having a plurality of function blocks respectively corresponding to a plurality of power supply voltages and an apparatus for generating layout data of such semiconductor device.
A large-scale integration (LSI) circuit, such as an application-specific integrated circuit (ASIC), includes function blocks, level converters, and repeater cells. The function blocks are driven by different power supply voltages. The level converter cells and the repeater cells are arranged in a plurality of line nets in correspondence with the power supply voltages. There is a demand that the layout designing of the LSI, including the layout designing of the level converter cells, the repeater cells, and the wiring, be performed more efficiently and within a shorter period of time.
FIG. 1 is a schematic plan view showing a prior art semiconductor device 80. The semiconductor device 80 has a substrate 81 on which seven function blocks 82, 83, 84, 85, 86, 87, 88 are defined. When each of the function blocks 82-88 have a power supply voltage that differs from that of the other function blocks, a line net connected to the function block is provided with a level converter cell (not shown).
FIG. 2 is a table indicating the power supply voltages of the function blocks 82-85 and positions where the level converter cells are required. The power supply voltage of the function block 82 (block A), the function block 83 (block B), function block 84 (block C), and function block 84 (block D) are 1.0V, 1.2V, 1.2V, and 0.8V, respectively. Except for the line net connecting the function blocks 83, 84, a level converter cell is required in each of the line nets connecting two function blocks. For example, a level converter cell is required in the line net connecting blocks A and B.
FIG. 3 is a schematic view showing a prior art step-up voltage level converter cell 90. The step-up voltage level converter cell 90 is connected to a line net between the function block of a low power supply voltage and the function block of a high power supply voltage. The step-up voltage level converter cell 90 includes a low voltage cell 90a, which is connected to the low voltage function block, and a high voltage cell 90b, which is connected to the high voltage function block. The low voltage cell 90a includes power supply terminals VDDL, VSS, and the high voltage cell 90b includes power supply terminals VDDH, VSS. The step-up voltage level converter cell 90 increases the voltage provided to the power supply terminal VDDL of the low voltage cell 90a and outputs the increased voltage from the power supply terminal VDDH of the high voltage cell 90b. It is preferred that the low voltage and high voltage cells 90a, 90b be proximal to each other.
FIG. 4 is a schematic diagram showing a prior art semiconductor device having a plurality of function blocks 91, 92, 93, 94 and a plurality of step-up voltage level converter cells 95, 96, 97 arranged between the blocks. The power supply voltages of the function blocks 91-94 are 1.0V, 1.2V, 1.2V, and 0.8V, respectively.
The step-up voltage level converter cell 95 is arranged in a line net between the function blocks 91, 92. The step-up voltage level converter 95 includes a low voltage cell 95a and a high voltage cell 95b. The step-up voltage level converter cell 95 increases the voltage of the low voltage cell 95a from 1.0V to 1.2V and outputs the increased voltage from the high voltage cell 95b. A standard cell (repeater cell) 98 is arranged between the low voltage cell 95a and the function block 91, and a standard cell 99 is arranged between the high voltage cell 95b and the function block 92. The repeater cell 98 receives the power supply voltage of the function block 91 (1.0V) and provides the voltage to the low voltage cell 95a. The repeater cell 98 receives the output voltage of the high voltage cell 95b (1.2V) and provides the voltage to the function block 92.
The step-up voltage level converter cell 96 is connected to a line net between the function blocks 91, 93. The step-up voltage level converter cell 96 increases the voltage provided to its low voltage cell 96a from 1.0V to 1.2V and outputs the increased voltage from its high voltage cell 96b. 
The step-up voltage level converter cell 97 is connected to a line net between the function blocks 91, 94. The step-up voltage level converter cell 97 increases the voltage provided to its low voltage cell 97a from 0.8V to 1.0V and outputs the increased voltage from its high voltage cell 97b. In this line net, a repeater cell 100 is arranged between the low voltage cell 97a and the function block 94, and a repeater cell 101 is arranged between the high voltage cell 97b and the function block 91. The repeater cell 100 provides the power supply voltage of the function block 94 (0.8V) to the low voltage cell 97a. The repeater cell 101 provides the output voltage of the high voltage cell 97b (1.0V) to the function block 91.
When designing the semiconductor device, it is preferred that power supply terminals receiving the same voltage be aligned with each other and be connected by a line having the same width.
However, referring to FIG. 3, the power supply terminal VDDL of the low voltage cell 90a is formed next to the power supply terminal VDDH of the high voltage cell 90b in the prior art step-up voltage level converter cell 90. Accordingly, in the semiconductor device of FIG. 4, the step-up voltage level converters 95-97 are separated into low voltage cells 95a, 96a, 97a and high voltage cells 95b, 96b, 97b. Further, among the low voltage cells 95a, 96a, 97a and the high voltage cells 95b, 96b, 97b, cells having the same power supply voltage are aligned with each other. The power supply voltage supplied by the repeater cell 99 (1.2V) differs from the power supply voltage supplied to the repeater cell 100 (0.8V). Thus, the repeater cells 99, 100 are not aligned with each other.
Accordingly, the designing of a multiple power supply semiconductor device is complicated due to the restrictions applied in relation with the power supply voltage of cells.